Taha Saadoon, A. (2013). Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl. Alustath, 19(3), 331-341.
Asma Taha Saadoon. "Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl". Alustath, 19, 3, 2013, 331-341.
Taha Saadoon, A. (2013). 'Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl', Alustath, 19(3), pp. 331-341.
Taha Saadoon, A. Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl. Alustath, 2013; 19(3): 331-341.

Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl

Journal of Engineering
Article 1, Volume 19, Issue 3, March 2013, Pages 331-341
Author
Asma Taha Saadoon
Abstract
It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.
Keywords
binary to decimal converter; FPGA; Verilog HDL; seven segment display; Cyclone II de; verilog
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