Design and Implementation of Neural Network in FPGA | ||
| Journal of Engineering and Sustainable Development | ||
| Article 1, Volume 16, Issue 3, September 2012, Pages 73-90 | ||
| Author | ||
| Rana D. Abdu-Aljabar | ||
| Abstract | ||
| This paper constructs fully parallel NN hardware architecture, FPGA has been used to reduce neuron hardware by design the activation function inside the neuron without using lookup table as in most researches, to perform an efficient NN. It consist of two main parts; the first part covers network training using MATLAB program, the second part represents the hardware implementation of the trained network through Xilinx high performance Virtex2 FPGA schematic entry design tools. | ||
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