Design and Implementation of a Network on Chip Using FPGA(English) | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 15, Volume 21, Issue 1, February 2013, Pages 91-100 PDF (0 K) | ||
| DOI: 10.33899/rengj.2013.67356 | ||
| Authors | ||
| Dr. A. I. A. Jabbar; Noor .Th. AL Malah | ||
| Abstract | ||
| Abstract The fundamental unit of building a Network on Chip is the router , it directs the packets according to a routing algorithm to the desired host. In this paper ,a router is designed using VHDL language and implemented on Spartan 3E FPGA with the help of Integrated software environment ( ISE10.1) . The utilization of the Spartan 3E resources is excellent ( for example the number of slices required doesn’t exceed 3%) .After that a (4×4) mesh topology network is designed and implemented using FPGA ( the number of slices is 43% of the available slices ) . An example is applied on the designed Network on Chip (NoC) which validates the design successfully . Keywords: Router , SoC, NoC, VHDL, FPGA,VGA,MESH | ||
| Keywords | ||
| KEYWORDS; SoC; NoC; VHDL; FPGA; VGA; MESH | ||
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