Implementation of Encoding Circuit for Inverse Differential Manchester Code (IDMC) And Clock Recovery Circuit | ||
| Al-Rafidain Engineering Journal (AREJ) | ||
| Article 7, Volume 20, Issue 1, February 2012, Pages 27-37 PDF (0 K) | ||
| DOI: 10.33899/rengj.2012.47151 | ||
| Author | ||
| Warqaa Youns Ibraheem | ||
| Abstract | ||
| Abstract In this research an inverse differential Manchester code (IDMC) circuit is implemented to encode random data using logical circuits, and clock recovery circuit is implemented too. A design of the first stage of clock recovery circuit which represents an edge detector circuit has been implemented using two one-shot mono-stable )74121( to detect the rising and falling edges respectively. The two circuits are tested practically at a low bit rate (1Kb/s) to study there operations. The encoding and clock recovery processes observed using oscilloscope. A comparison is made using simulation program (MATLAB 7.4 ) with the practical results and they were close to simulation results. The encoded circuit has been tested at (5Mb/s) which is lying in Token ring LAN range. In this research a practical illustration of the effectiveness of high pass filtering on random data has been made and compared with IDMC encoded data, this comparison improve the advantages of line code that have dc balance and high transition density which are lack in the random data. Keywords: Line Code, Inverse Differential Manchester encoder circuit, clock recovery, practical implementation | ||
| Keywords | ||
| KEYWORDS; Inverse Differential Manchester encoder circuit; clock recovery; practical implementation | ||
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