Comparison between FPGA Co-Processor &Tms320 C641x DSP Family in Implementing DIF FFT Algorithm | ||
| Journal of Engineering | ||
| Article 1, Volume 11, Issue 3, September 2005, Pages 533-540 | ||
| Authors | ||
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| Abstract | ||
| The Decimation in Frequency Fast Fourier Transform (DIF FFT) is a computationally intensive digital signal processing function widely used in application such as imaging and wireless communication .Historically, this has been a relatively difficult function to implement optimally in hardware, leading many software designers to use digital signal processors (DSPs) in soft implementations. Unfortunately, because of the function s computationally intensive nature, such an approach typically requires multiple DSPs within the system to support the processing requirements. This is costly from a device and board rcal – estate perspective as well as power intensive. Field –programmable gate array (FPGA) co-processors have become an extremely cost – effective means of off – loading computationally intensive algorithms to improve overall system performance while reducing development time, cost and risks. This paper will describe two DIF FFT implementation approaches, one implemented as an FPGA co –processor and the other using only an external TMS320C641X DSP Family. It will then examine the advantages and disadvantages of implementation perspectives. | ||
| Keywords | ||
| FFT; FPGA; DSPs; SimplestImplementation; Cost; W Parallelism; power consumption | ||
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