Dynamic Power Consumption In CMOS N Bit Full-Adder Circuit | ||
| Engineering and Technology Journal | ||
| Article 7, Volume 39, 5A, May 2021, Pages 754-767 PDF (599.97 K) | ||
| Document Type: Research Paper | ||
| DOI: 10.30684/etj.v39i5A.1846 | ||
| Authors | ||
| Amal F. Hasan* 1; Qusay F. Al-Doori2 | ||
| 1Control and Systems Engineering Department, University of Technology - Iraq | ||
| 2Control and Systems Eng., University of Technology - Iraq | ||
| Abstract | ||
| This paper discusses power consumption in the full adder circuit using some fabrication technologies. Though many studies related to power consumption in the full adder circuit were performed, however, few investigations about the effect of the number of bits on the power consumption are addressed. In this paper, the effect of changing the number of bits on the power consumption and time delay of the full adder circuit will be observed and the effect of changing the technology size is going to be calculated. The results will show that there is a direct relationship between the number of bits and power. | ||
| Keywords | ||
| CMOS; Dynamic power; Full adder | ||
|
Statistics Article View: 243 PDF Download: 337 |
||