FPGA Design and Implementation of Data Covering Based on MD5 Algorithm | ||
| Engineering and Technology Journal | ||
| Article 7, Volume 34, 14A, December 2016, Pages 2621-2630 PDF (924.3 K) | ||
| DOI: 10.30684/etj.34.14A.7 | ||
| Author | ||
| Thamir R. Saeed | ||
| Abstract | ||
| The protection of information leads to protection of individual privacy for everyone. This protection is performed using encryption. Many types of encryption may be utilized while the simplest one is the covering of information. In this paper, three novel algorithms have been presented for covering the information and for increasing the security. The degree of these security algorithms depends on three keys; MD5 core code, MD5 iteration, and mode of data hashing. The strengths of this work are the simplicity of the design and taken a long time for attack recovering the hashing data. Where, the sequence length for our proposed algorithms related to the MD5 output sequence length will be increased from 100% for 8-bit core code to 256% for scenarios E and F, while 1024% for scenario G with processing time is 20 nsec and 60 nsec depend on the scenarios. While the bit rate of the information data in transmitted data stream bits are different from 64-to- 32 bits for each transmitted stream bits depending on the scenario that selected. In this context, the maximum expected throughput is 806.596 Mbps. The implementation of algorithm circuits is built by using Xilinx Spartan 3-xc3s1400a-4fg484. | ||
| Keywords | ||
| VHDL; FPGA; Spartan; Hashing data; and MD | ||
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