Hardware Implementation of Artificial Neural Network for Data Ciphering | ||
| Tikrit Journal of Engineering Sciences | ||
| Article 1, Volume 23, Issue 2, June 2016, Pages 74-85 PDF (0 K) | ||
| Authors | ||
| Sahar L. Kadoory; Toka A. Fatehi; Qutaiba A. Hasan | ||
| Abstract | ||
| This paper introduces the design and realization of multiple blocks ciphering techniques on the FPGA (Field Programmable Gate Arrays). A back propagation neural networks have been built for substitution, permutation and XOR blocks ciphering using Neural Network Toolbox in MATLAB program. They are trained to encrypt the data, after obtaining the suitable weights, biases, activation function and layout. Afterward, they are described using VHDL and implemented using Xilinx Spartan-3E FPGA using two approaches: serial and parallel versions. The simulation results obtained with Xilinx ISE 9.2i software. The numerical precision is chosen carefully when implementing the Neural Network on FPGA. Obtained results from the hardware designs show accurate numeric values to cipher the data. As expected, the synthesis results indicate that the serial version requires less area resources than the parallel version. As, the data throughput in parallel version is higher than the serial version in rang between (1.13-1.5) times. Also, a slight difference can be observed in the maximum frequency. | ||
| Keywords | ||
| Back Propagation; Ciphering; encryption; FPGA; neural network; VHDL | ||
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