Complete Neural Network on a Single FPGA Chip | ||
| Journal of Engineering and Sustainable Development | ||
| Article 1, Volume 14, Issue 3, September 2010, Pages 53-69 | ||
| Author | ||
| Dhafer R. Zaghar | ||
| Abstract | ||
| This paper presents a hardware implementation approach for Neural Networks (NNs) on a Programmable System-On-Chip. This is an intrinsic online evolution system that can be genetically evolved and adapted to change in input data patterns dynamically without any need for multiple Field Programmable Gate Array (FPGA) reconfigurations to accommodate various network structure/parameter changes. This will remove a considerable bottleneck for performance. The hardware implementation of NN using FPGA has two main problems. First it is required a large cost because it has a large number of multipliers, lock up tables (LUTs) and adders. Second the additional error that generate from the truncation of numbers when each value in software has minimum 64-bit while it has in hardware maximum 16-bit. This paper discusses combinations methods to reduce the cost and increase the speed of NN and propose a novel approaches to removes a considerable bottleneck and reduce the cost of a NN to plausible range under FPGA hardware. | ||
| Keywords | ||
| neural networks; System; Chip; FPGA; multiplier; carry lookahead adder; ripple adder; activation function; LUT; piecewise | ||
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